Larger system chips often include analog as well as digital circuits. Signals may cross from the digital domain to the analog domain, and vice-versa. Analog signals may be converted to digital for complex digital processing, such as by a Digital Signal Processor (DSP).
Many types of Analog-to-Digital Converters (ADC's) have been used for a wide variety of applications. Flash ADC's compare analog signal voltages to multiple voltage levels in an instant to produce a multi-bit digital word that represents the analog voltage. Successive-approximation ADC's use a series of stages to convert an analog voltage to digital bits. Each stage compares an analog voltage to a reference voltage, producing one digital bit. In sub-ranging ADC's, each stage compares an analog voltage to several voltage levels, so that each stage produces several bits. Succeeding stages generate lower-significant digital bits than do earlier stages in the pipeline.
Algorithmic, re-circulating, or recycling ADC's use a loop to convert an analog voltage. The analog voltage is sampled and compared to produce a most-significant digital bit. Then the digital bit is converted back to analog and subtracted from the analog voltage to produce a residue voltage. The residue voltage is then multiplied by two and looped back to the comparator to generate the next digital bit. Thus the digital bits are generated over multiple cycles in the same comparator stage.
FIG. 1 shows a Successive-Approximation-Register ADC. Successive-Approximation-Register SAR 102 receives a clock CLK and contains a register value that is changed to gradually zero-in on a close approximation of the analog input voltage VIN. For example, the value in SAR 102 may first be 0.5, then 0.25, then 0.375, then 0.312, then 0.281, then 0.296, then 0.304, then 0.308, then 0.31, then 0.311, and finally 0.312 when comparing to a VIN of 0.312 volts. SAR 102 outputs the current register value to digital-to-analog converter (DAC) 100, which receives a reference voltage VREF and converts the register value to an analog voltage VA.
The input analog voltage VIN is applied to sample-and-hold circuit 104, which samples and holds the value of VIN. For example, a capacitor can be charged by VIN and then the capacitor isolated from VIN to hold the analog voltage. The sampled input voltage from sample-and-hold circuit 104 is applied to the inverting input of comparator 106. The converted analog voltage VA is applied to the non-inverting input of comparator 106.
Comparator 106 compares the converted analog voltage VA to the sampled input voltage and generates a high output when the converted analog voltage VA is above the sampled VIN, and the register value in SAR 102 is too high. The register value in SAR 102 can then be reduced.
When the converted analog voltage VA is below the sampled input voltage, comparator 106 generates a low output to SAR 102. The register value in SAR 102 is too low. The register value in SAR 102 can then be increased for the next cycle.
The register value from SAR 102 is a binary value of N bits, with D(N−1) being the most-significant-bit (MSB) and D0 being the least-significant-bit (LSB). SAR 102 can first set the MSB D(N−1), then compare the converted analog voltage VA to the input voltage VIN, then adjust the MSB and/or set the next MSB D(N−2) based on the comparison. The set and compare cycle repeats until after N cycles the LSB is set. After the last cycle, the end-of-cycle EOC signal is activated to signal completion. A state machine or other controller can be used with or included inside SAR 102 to control sequencing.
DAC 100 or sample-and-hold circuit 104 may have an array of capacitors. The capacitors have binary-weighted values, such as 1, 2, 4, 8, 16, 32, . . . times a minimum capacitor size. For example, a 6-bit DAC may have an array of capacitors of 1, 2, 4, 8, 16, 32 times a minimum capacitance C. Higher-resolution DAC's such as a 11-bit DAC have much larger capacitor values, such as 2N−1=1024.
While such capacitor-array DAC's are useful, the large size of the MSB capacitors requires a large amount of charge to be transferred. The total capacitance Ct of a binary-weighted capacitor array is 2N*C, where N is the number of binary bits and C is the capacitance of the minimum capacitor.
The dynamic power requirements of the DAC portion of the ADC increase as total capacitance Ct of the capacitor array increases, since dynamic power is f*Ct*V2 for a frequency f and a voltage swing V.
The minimum capacitor size C can be shrunk to reduce the overall capacitance of the capacitor array and thus reduce the dynamic power requirements. The minimum capacitor size may be restricted by the process technology. For example, a sub-micron process may allow for a 4×4 μm2 minimum physical-size for a metal-to-metal capacitor, which has a capacitance of about 16 fF.
The minimum total capacitor size for sample and hold switches used in a data converter is limited by the thermal noise (KT/C), which must be smaller than the quantization noise
      (                            Δ          2                12            =                                    (                          Vdd              /                              2                N                                      )                    2                /        12              )    ,where N is the number of bits, and Vdd is the power supply voltage. For example, a 1V supply, 12-bit ADC has a quantization noise of about 5E-9, and thus the required capacitor for thermal noise is much larger than 0.805 pF, so that the thermal noise is lower than the quantization noise.
The quantization noise limit
  (            Δ      2        12    )can be increased by reducing the number of bits in the capacitor array. For example, a 1V supply, 10-bit array has a quantization noise limit of 79.5 nV2, while an 8-bit ADC has a quantization noise about 1.27 uV2. Although thermal noise is increased by removing MSBs from the binary-weighted capacitor array, the total capacitor size can be reduced significantly. For an example, when the 2 MSB capacitors are removed, which are the largest capacitors, Ct drops from 212 to 210 C. Thus smaller binary-weighted capacitor arrays have lower capacitance due to removing the MSB capacitors.
Thermal noise is increased by removing the MSBs from the binary-weighted capacitor array until the thermal noise contributed by the capacitors is slight less than or reaches the theoretical limit of quantization noise of the required resolution.
What is desired is an ADC with reduced total capacitance to reduce dynamic power. A capacitor array for a SAR ADC is desirable that has a smaller binary-weighted capacitor array to reduce capacitance, yet still achieves a target resolution. An ADC with both a reduced-size binary-weighted capacitor array and a sub-voltage capacitor array is desirable.